The USB standard is based on a technical specification detailing communications between a host controller (such as a personal computer) and a device, for example a keyboard, a mouse, a digital camera, an external memory, etc., via an interface called a USB port. The USB 2.0 standard defines different data transfer rates, including a low rate mode at 1.5 Mb/s with a margin of accuracy of ±1.5%, and a full rate at 12 Mb/s with a margin of accuracy of ±0.25%.
As the host controller does not send any clock signal to the device, the device must generate its own clock signal with sufficient accuracy to comply with the required USB data transfer rate. A quartz crystal oscillator may be provided, but this solution is not suitable for low-cost applications and takes up too much space. An alternative solution is to base the generation of clock cycles on a synchronization signal sent by the host, for example a frame start signal or a “Keep Alive” maintenance signal sent in the absence of traffic to prevent the device from switching to idle state. In this case, the time interval between two consecutive synchronization signals is 1 ms. For a USB device operating at low rate, with a clock frequency of 6 MHz, a margin of accuracy of ±1.5% gives a frequency margin of ±90 KHz, giving between 5,910 and 6,090 clock cycles per time interval of 1 ms. For a USB device operating at full rate, with a clock frequency of 48 MHz, a margin of accuracy of ±0.25% gives a frequency margin of ±120 KHz, giving between 47,880 and 48,120 clock cycles per time interval of 1 ms.
FIG. 1 shows a clock frequency adjusting circuit 1 comprising an oscillator OSC and a calibration unit CAL. The oscillator OSC generates a clock signal CLK that is supplied to the calibration unit CAL. When the calibration unit CAL receives a first occurrence of a synchronization signal SNC, it starts counting the number of cycles of the clock signal CLK at its input until the next occurrence of the synchronization signal, when it stops counting. The calibration unit CAL determines the difference between the counted number of cycles and the desired number of cycles, then supplies the oscillator OSC with a control signal S, that increases or decreases its frequency accordingly.
It transpires that the frequency jump at output of the oscillator OSC resulting from the application of the control signal S is unknown. Indeed, the operation of the oscillator may vary with time, for example due to a variation in temperature or supply voltage, altering the operation of the oscillator. Thus, the frequency obtained at output of the oscillator may be too high or too low after the first adjustment phase.
The number of clock cycles is thus counted again upon the next time interval so as to determine the frequency pitch of the oscillator. The calibration unit CAL again supplies the oscillator OSC with the control signal S to obtain the desired frequency after the second time interval.
The application FR 2 978 258 (US 2013/0021106) describes a clock frequency adjusting circuit comprising two identical oscillators generating a clock signal the frequency of which can be adjusted by delay lines according to a control value, and a circuit configured to measure the frequency of each of the two oscillators, and determine new control values using the frequency measurements and the previous control values, and a desired frequency value. The accuracy of this frequency adjusting circuit depends on the identity of the behavior of the two oscillators. It can be seen that by increasing their frequency, the oscillators have diverging behaviors. Thus, this circuit offers an accuracy that may prove insufficient for certain transmission protocols. Such a divergence is also seen with the recent manufacturing technologies making it possible to further miniaturize integrated circuits. In particular, when the critical dimension (or the smallest transistor gate width) of the integrated circuit is lower than 100 nm, it is difficult to limit the divergences of features of oscillators to acceptable values, even if they are in a same integrated circuit.
It also transpires that the more the frequency of the oscillators is increased, the higher variations in frequency are induced by variations in circuit manufacturing conditions, ambient temperature and supply voltage, and thus the more the number of cycles necessary to reach the desired frequency increases.
The result is that in many applications, particularly data transmission applications, this solution does not enable the desired frequency to be reached sufficiently rapidly or accurately. In particular, this solution is not suitable for a USB device operating at full speed, i.e. with a clock signal at 48 MHz.
It is thus desirable to propose a clock circuit susceptible of being totally integrated, i.e. not requiring any components such as a quartz crystal. It is also desirable for this clock circuit to be rapidly able to reach a desired frequency, even if this frequency is high, and if the clock circuit is produced in accordance with the latest integrated circuit manufacturing technologies. It is also desirable for the desired frequency to be reached with sufficient accuracy.